TESTCHIP: a chip for weighted random pattern generation, evaluation, and test control

In self-testable circuits, additional hardware is incorporated for generating test patterns and evaluating test responses. A built-off test strategy is presented which moves the additional hardware to a programmable extra chip. This is a low-cost test strategy in three ways: (1) the use of random patterns eliminates the expensive test-pattern computation; (2) a microcomputer and an ASIC (application-specific IC) replace the expensive automatic test equipment; and (3) the design for testability overhead is minimized. The presented ASIC generates random patterns, applies them to a circuit under test, and evaluates the test responses by signature analysis. It contains a hardware structure that can produce weighted random patterns corresponding to multiple programmable distributions. These patterns give a high fault coverage and allow short test lengths. A wide range of circuits can be tested as the only requirement is a scan path and no other test structures have to be built in

A unified method for assembling global test schedules

In order to make a register transfer structure testable, it is usually divided into functional blocks that can be tested independently by various test methods. The test patterns are shifted in or generated autonomously at the inputs of each block. The test responses of a block are compacted or observed at its output register. In this paper a unified method for assembling all the single tests to a global schedule is presented. It is compatible with a variety of different test methods. The described scheduling procedures reduce the overall test time and minimize the number of internal registers that have to be made directly observable

Signature analysis and test scheduling for self-testable circuits

In complex circuits the test execution is usually divided into a number of subtasks, each producing a signature in a self-test register. These signatures influence one another. A model that can be used as a basis for test scheduling procedures is presented, and it is shown how test schedules can be constructed, in order to minimize the number of signatures to be evaluated. The error masking probabilities decrease when the subtasks of the test execution are repeated in an appropriate order, and an equilibrium situation is reached where the error masking probabilities are minimal. A method is presented for constructing test schedules so that only the signatures at the primary outputs must be evaluated to get a sufficient fault coverage. Then no internal scan path is required, only a few signatures have to be evaluated at the end of the test execution, and the test control at chip and board level is simplified. The amount of hardware to implement a built-in self-test is reduced significantly

Maximizing the fault coverage in complex circuits by minimal number of signatures

Methods to minimize the number of evaluated signatures without reducing the fault coverage are presented. This is possible because the signatures can influence one another during the test execution. For a fixed test schedule a minimal subset of signatures can be selected, and for a predetermined minimal subset of signatures the test schedule can be constructed such that the fault coverage is maximum. Both approaches result in significant hardware savings when a self-test is implemented

Error masking in self-testable circuits

The effects of error masking in a number of signature registers are analyzed. It is shown that a self-test can always be scheduled such that evaluating signatures only at the end of the complete test execution is sufficient. A method for computing the probability of a fault leading to at least one faulty signature in a set of self-test registers is presented. This method allows the computation of the fault coverage with respect to the complete test execution. A minimal subset of all self-test registers can be selected so that only the signatures of these self-test registers have to be evaluated and the fault coverage is almost not affected. The benefits of this approach are a smaller number of self-test registers in the scan path, a smaller number of signatures to be evaluated, a simplified test control unit, and hence a significant reduction in tie hardware required for built-in self-test structures. The proposed method is illustrated by an example and validated by simulation

TESTCHIP: a chip for weighted random pattern generation, evaluation, and test control

A chip is presented that generates weighted random patterns, applies them to a circuit under test and evaluates the test responses. The generated test patterns correspond to multiple sets of weights. Test response evaluation is done by signature analysis. The chip can easily be connected to a micro computer and thus constitutes the key element of a low-cost test equipment